25 #ifndef _GLIBCXX_EXPERIMENTAL_SIMD_DETAIL_H_ 26 #define _GLIBCXX_EXPERIMENTAL_SIMD_DETAIL_H_ 28 #if __cplusplus >= 201703L 35 #define _GLIBCXX_SIMD_BEGIN_NAMESPACE \ 36 namespace std _GLIBCXX_VISIBILITY(default) \ 38 _GLIBCXX_BEGIN_NAMESPACE_VERSION \ 39 namespace experimental { \ 40 inline namespace parallelism_v2 { 41 #define _GLIBCXX_SIMD_END_NAMESPACE \ 44 _GLIBCXX_END_NAMESPACE_VERSION \ 49 #if defined __ARM_NEON 50 #define _GLIBCXX_SIMD_HAVE_NEON 1 52 #define _GLIBCXX_SIMD_HAVE_NEON 0 54 #if defined __ARM_NEON && (__ARM_ARCH >= 8 || defined __aarch64__) 55 #define _GLIBCXX_SIMD_HAVE_NEON_A32 1 57 #define _GLIBCXX_SIMD_HAVE_NEON_A32 0 59 #if defined __ARM_NEON && defined __aarch64__ 60 #define _GLIBCXX_SIMD_HAVE_NEON_A64 1 62 #define _GLIBCXX_SIMD_HAVE_NEON_A64 0 67 #define _GLIBCXX_SIMD_HAVE_MMX 1 69 #define _GLIBCXX_SIMD_HAVE_MMX 0 71 #if defined __SSE__ || defined __x86_64__ 72 #define _GLIBCXX_SIMD_HAVE_SSE 1 74 #define _GLIBCXX_SIMD_HAVE_SSE 0 76 #if defined __SSE2__ || defined __x86_64__ 77 #define _GLIBCXX_SIMD_HAVE_SSE2 1 79 #define _GLIBCXX_SIMD_HAVE_SSE2 0 82 #define _GLIBCXX_SIMD_HAVE_SSE3 1 84 #define _GLIBCXX_SIMD_HAVE_SSE3 0 87 #define _GLIBCXX_SIMD_HAVE_SSSE3 1 89 #define _GLIBCXX_SIMD_HAVE_SSSE3 0 92 #define _GLIBCXX_SIMD_HAVE_SSE4_1 1 94 #define _GLIBCXX_SIMD_HAVE_SSE4_1 0 97 #define _GLIBCXX_SIMD_HAVE_SSE4_2 1 99 #define _GLIBCXX_SIMD_HAVE_SSE4_2 0 102 #define _GLIBCXX_SIMD_HAVE_XOP 1 104 #define _GLIBCXX_SIMD_HAVE_XOP 0 107 #define _GLIBCXX_SIMD_HAVE_AVX 1 109 #define _GLIBCXX_SIMD_HAVE_AVX 0 112 #define _GLIBCXX_SIMD_HAVE_AVX2 1 114 #define _GLIBCXX_SIMD_HAVE_AVX2 0 117 #define _GLIBCXX_SIMD_HAVE_BMI1 1 119 #define _GLIBCXX_SIMD_HAVE_BMI1 0 122 #define _GLIBCXX_SIMD_HAVE_BMI2 1 124 #define _GLIBCXX_SIMD_HAVE_BMI2 0 127 #define _GLIBCXX_SIMD_HAVE_LZCNT 1 129 #define _GLIBCXX_SIMD_HAVE_LZCNT 0 132 #define _GLIBCXX_SIMD_HAVE_SSE4A 1 134 #define _GLIBCXX_SIMD_HAVE_SSE4A 0 137 #define _GLIBCXX_SIMD_HAVE_FMA 1 139 #define _GLIBCXX_SIMD_HAVE_FMA 0 142 #define _GLIBCXX_SIMD_HAVE_FMA4 1 144 #define _GLIBCXX_SIMD_HAVE_FMA4 0 147 #define _GLIBCXX_SIMD_HAVE_F16C 1 149 #define _GLIBCXX_SIMD_HAVE_F16C 0 152 #define _GLIBCXX_SIMD_HAVE_POPCNT 1 154 #define _GLIBCXX_SIMD_HAVE_POPCNT 0 157 #define _GLIBCXX_SIMD_HAVE_AVX512F 1 159 #define _GLIBCXX_SIMD_HAVE_AVX512F 0 162 #define _GLIBCXX_SIMD_HAVE_AVX512DQ 1 164 #define _GLIBCXX_SIMD_HAVE_AVX512DQ 0 167 #define _GLIBCXX_SIMD_HAVE_AVX512VL 1 169 #define _GLIBCXX_SIMD_HAVE_AVX512VL 0 172 #define _GLIBCXX_SIMD_HAVE_AVX512BW 1 174 #define _GLIBCXX_SIMD_HAVE_AVX512BW 0 177 #if _GLIBCXX_SIMD_HAVE_SSE 178 #define _GLIBCXX_SIMD_HAVE_SSE_ABI 1 180 #define _GLIBCXX_SIMD_HAVE_SSE_ABI 0 182 #if _GLIBCXX_SIMD_HAVE_SSE2 183 #define _GLIBCXX_SIMD_HAVE_FULL_SSE_ABI 1 185 #define _GLIBCXX_SIMD_HAVE_FULL_SSE_ABI 0 188 #if _GLIBCXX_SIMD_HAVE_AVX 189 #define _GLIBCXX_SIMD_HAVE_AVX_ABI 1 191 #define _GLIBCXX_SIMD_HAVE_AVX_ABI 0 193 #if _GLIBCXX_SIMD_HAVE_AVX2 194 #define _GLIBCXX_SIMD_HAVE_FULL_AVX_ABI 1 196 #define _GLIBCXX_SIMD_HAVE_FULL_AVX_ABI 0 199 #if _GLIBCXX_SIMD_HAVE_AVX512F 200 #define _GLIBCXX_SIMD_HAVE_AVX512_ABI 1 202 #define _GLIBCXX_SIMD_HAVE_AVX512_ABI 0 204 #if _GLIBCXX_SIMD_HAVE_AVX512BW 205 #define _GLIBCXX_SIMD_HAVE_FULL_AVX512_ABI 1 207 #define _GLIBCXX_SIMD_HAVE_FULL_AVX512_ABI 0 210 #if defined __x86_64__ && !_GLIBCXX_SIMD_HAVE_SSE2 211 #error "Use of SSE2 is required on AMD64" 216 #define _GLIBCXX_SIMD_NORMAL_MATH 218 #define _GLIBCXX_SIMD_NORMAL_MATH \ 219 [[__gnu__::__optimize__("finite-math-only,no-signed-zeros")]] 221 #define _GLIBCXX_SIMD_NEVER_INLINE [[__gnu__::__noinline__]] 222 #define _GLIBCXX_SIMD_INTRINSIC \ 223 [[__gnu__::__always_inline__, __gnu__::__artificial__]] inline 224 #define _GLIBCXX_SIMD_ALWAYS_INLINE [[__gnu__::__always_inline__]] inline 225 #define _GLIBCXX_SIMD_IS_UNLIKELY(__x) __builtin_expect(__x, 0) 226 #define _GLIBCXX_SIMD_IS_LIKELY(__x) __builtin_expect(__x, 1) 228 #if defined __STRICT_ANSI__ && __STRICT_ANSI__ 229 #define _GLIBCXX_SIMD_CONSTEXPR 230 #define _GLIBCXX_SIMD_USE_CONSTEXPR_API const 232 #define _GLIBCXX_SIMD_CONSTEXPR constexpr 233 #define _GLIBCXX_SIMD_USE_CONSTEXPR_API constexpr 236 #if defined __clang__ 237 #define _GLIBCXX_SIMD_USE_CONSTEXPR const 239 #define _GLIBCXX_SIMD_USE_CONSTEXPR constexpr 242 #define _GLIBCXX_SIMD_LIST_BINARY(__macro) __macro(|) __macro(&) __macro(^) 243 #define _GLIBCXX_SIMD_LIST_SHIFTS(__macro) __macro(<<) __macro(>>) 244 #define _GLIBCXX_SIMD_LIST_ARITHMETICS(__macro) \ 245 __macro(+) __macro(-) __macro(*) __macro(/) __macro(%) 247 #define _GLIBCXX_SIMD_ALL_BINARY(__macro) \ 248 _GLIBCXX_SIMD_LIST_BINARY(__macro) static_assert(true) 249 #define _GLIBCXX_SIMD_ALL_SHIFTS(__macro) \ 250 _GLIBCXX_SIMD_LIST_SHIFTS(__macro) static_assert(true) 251 #define _GLIBCXX_SIMD_ALL_ARITHMETICS(__macro) \ 252 _GLIBCXX_SIMD_LIST_ARITHMETICS(__macro) static_assert(true) 254 #ifdef _GLIBCXX_SIMD_NO_ALWAYS_INLINE 255 #undef _GLIBCXX_SIMD_ALWAYS_INLINE 256 #define _GLIBCXX_SIMD_ALWAYS_INLINE inline 257 #undef _GLIBCXX_SIMD_INTRINSIC 258 #define _GLIBCXX_SIMD_INTRINSIC inline 261 #if _GLIBCXX_SIMD_HAVE_SSE || _GLIBCXX_SIMD_HAVE_MMX 262 #define _GLIBCXX_SIMD_X86INTRIN 1 264 #define _GLIBCXX_SIMD_X86INTRIN 0 271 #define _GLIBCXX_SIMD_USE_ALIASING_LOADS 1 274 #if _GLIBCXX_SIMD_X86INTRIN 275 #define _GLIBCXX_SIMD_WORKAROUND_PR85048 1 279 #define _GLIBCXX_SIMD_WORKAROUND_PR90993 1 283 #if _GLIBCXX_SIMD_X86INTRIN 284 #define _GLIBCXX_SIMD_WORKAROUND_XXX_1 1 288 #define _GLIBCXX_SIMD_WORKAROUND_PR90424 1 291 #if _GLIBCXX_SIMD_X86INTRIN 292 #define _GLIBCXX_SIMD_WORKAROUND_XXX_3 1 297 #define _GLIBCXX_SIMD_FIX_P2TS_ISSUE65 1 301 #define _GLIBCXX_SIMD_FIX_P2TS_ISSUE66 1 306 #endif // __cplusplus >= 201703L 307 #endif // _GLIBCXX_EXPERIMENTAL_SIMD_DETAIL_H_